Infineon Technologies Pvt Ltd

Senior Elect Design Engineer

Infineon Technologies Pvt Ltd
Not Disclosed
1-3 Years Full Time
Bangalore, Karnataka, IN

Vacancy: Not Disclosed Posted: 1 year ago Applicants: 0
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Job Description

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  • Candidate should have working experience with AMS Verification on multiple SOCor sub-systems
  • One should have proficiency in AMS simulation environment using Cadence\/Synopsys\/Mentor tools
  • Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus
  • Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS)
  • Experience in SV and UVM testbench development\/modifications from mixed signal perspective is a plus
  • Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected
  • Working knowledge of Perl \/ Skill\/ Python\/Tcl or other scripting relevant language is a plus
  • Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment

    Measurement Criteria:
    • Behavioral modeling: Verilog, Wreal or SV-RNM -Full
      AMS Verification for SoC or IPs -Full
    • Test plan preparation as per the dynamics of product specifications - Partial
    • Dealing challenges with AMS methodologies of Cadence: irun\/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial
    • Testcase Debug proposing new scenarios
    • Handling project dynamics on scope, schedule and effort coming up with alternative verification plans, Mentoring Junior engineer

Candidate profile:

Bachelors with 3 years or Masters with 2 years of experience

Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage

HDL / HVL: Verilog / Verilog-ams, SV / UVM added advantage

Tools: Cadence Xcelium spectre / Synopsys XA-VCS / Mentor Eldo ADMS

Automation: Perl / python / shell

  • Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements

Skills Required: Automation, Simulation


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