Qualcomm Technologies, Inc

RTL: Design Engineer - Serdes/PHY

Qualcomm Technologies, Inc
Not Disclosed
2-7 Years Full Time
Bangalore, Karnataka, IN

Vacancy: Not Disclosed Posted: 1 month ago Applicants: 0
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Job Description

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Responsibilities include:

  • Digital design for PLL, DAC, ADC, LDO, APM, and other mixed-signal designs.
  • Digital design aspects include full behavioral level description with high level synthesis languages and gate level synthesis, logic level synthesis, timing closure, power and signal integrity analysis and testability.
  • Work in a dynamic team environment with aggressive schedule, chip power consumption and area targets.

Minimum Qualifications

  • Bachelors degree in Science, Engineering, or related field.
  • 3 years ASIC design experience
  • Digital ASIC design including architecture
  • RTL design for control and datapath, linting, synthesis, FV, STA, and DFT
  • Experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence
  • Should possess good communication skills to ensure effective interaction with Management and team members.
  • Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision

Education Requirements:

  • Bachelors, Electronics / Electronics communication Engineering
    Preferred: Masters, Electronics / Electronics communication / VLSI Engineering

Skills Required: DFT,Packaging


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