Job
Description
IR Signoff CPU/high performance cores
Signal EM Power EM Signoff for Chip TOP level Block level CPU/DSP and other HM s
Development of PG Grid spec for different HM
Validating the PG Grid using Grid Resistance Secondary PG Resistance Checks
Validating the IR Drops using Static IR , Dynamic IR Vless VCD Checks for validating Die Pkg Components of IR Drops
Working with SOC and Packaging Teams on Bumps Assignments / RDL Enablement / Pkg Routing Optimizations to improve overall PDN Design
Good knowledge on PD would is desirable
Python , Perl , TCL
Skill Set
Hands on experience in PDN Signoff using Redhawk / RHSC / Voltus at block level / SOC Level.
Good understanding on Power Integrity Signoff Checks.
Proficient in scripting languages (Tcl and Perl).
Familiarity with Innovus for RDL / Bump Planning.
Ability to communicate effectively with multiple global cross-functional teams
Tools : Redhawk , Redhawk_SC and basic use case of Innovus/ Fusion Compiler
LSF /compute optimization understanding
Minimum Qualifications
Education:
Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems
Work Experiences:
2 years Hardware Engineering experience or related work experience.