Job Description

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• Responsible for developing backend ASIC design flow from netlist to gdsii & Physical verification for validating the std cell libraries .
• Also need to work on automation using perl and tcl for enhancing the design flow .

Requires:
- Bachelors or Masters degree in electronics or electrical engineering (B. Tech/M. Tech) or equivalent from reputed universities .
- Knowledge on VLSI technology
- Gate level and circuit level understanding of CMOS logic design.
- Experience in physical design implementation flow (floorplan, placement, CTS and routing)
- Scripting in Perl and TCL
- Understanding of timing and design closure aspects
- DRC/LVS understanding
- Good communication, interpersonal skills and team player

Skills Required: Automation, Backend, Interpersonal Skills