Job
Description
As Applications Engineer (Intern), you will be working on development and qualification of Synopsys tool IC Validators DRC/LVS/Fill runsets (rule deck for cutting edge technologies and leading foundries. Occasionally, you may also be involved in various automation activities to qualify the IC Validator runset.
Requirements:
- Person should have B.Tech/M.Tech/MS degree in Electronics/VLSI domain.
- Should have understanding and exposure to transistor CMOS layouts. Proficient with Perl/Tcl, Unix, HDL (Verilog/VHDL) and a strong understanding of ASIC design flow, VLSI, and/or CAD engineering.
- Knowledge of competitive EDA tool products like Calibre/Assura/PVS and product knowledge in any of the areas, like writing foundry decks ( DRC/LVS/ERC/DFM ), solving LVS issues, knowledge of foundry processes, understanding of cutting edge DFM requirements etc. is highly desired. The internship period is one year.