Job Description

Job Responsibilities:

• Analyze and identify design features to verify in formal method.
• Write checker in SVA to verify design properties.
• Run formal verification tools to prove or falsify formal properties.
• Generate waveform and work with design engineer to resolve design or checker issues.
• Generate coverage report and analyze verification coverage.

Requirements:

• BS/MS/PhD in Computer Science, Computer Engineering, or Electrical Engineering with 0-3 years of experience in digital design, or design verification.
• Solid understanding of Verilog and SystemVerilog Assertion (SVA).
• Experience in debugging tools such as Verdi and SimVision.
• Skillful in RTL coding of digital design.
• Good understanding of machine arithmetic.
• Skills in scripting language such as Perl, Tcl and Python is a plus.
• Experience in formal verification tools such as VCFormal or JasperGold is a huge plus.

Skills Required: Computer Science, Semiconductor