Develops and applies computer aided design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems. Assessing architecture and hardware limitations, plans technical projects in the design and development of CAD software. Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters. Develops routines and utility programs. Prepares design specifications, analysis and recommendations for presentation and approval. May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.
Skills Required: HTML,Java,MS Excel,MS Office
Job Description: Develop, test, deploy and maintain VLSI CAD Design automation tools and flows/scripts in the area of Logical Synthesis and Formal Equivalence verification. Design Automation Engineers are advocates of applying design methodologies to help execute projects effectively and successfully with high quality. As a CAD engineer you will be part of team who shall design, innovate, develop methodology and cater solutions to Intel SOC teams delivering projects to core and client Intel business. Responsibility: As a VLSI CAD engineer you will design, develop and optimize Full chip (SOC) Logic Synthesis flows and Formal equivalence verification related features based on internal customers' demands. You will be designing and implementing code related to advanced features for construction and verification in Synthesis tools and FEV for full chip level. You will also be working on performance analysis and tuning, with opportunity of influencing future CCCAD communities as well as R2G design TFM for the Client products Qualification Masters in Electronics Engineering / Computer Engineering with at least 8 years' experience Skill Set required Candidate should have at least 8 to 10 years hand-on expertise in all of the following domains - Experience in RTL design, Logical synthesis, UPF, STA, Formal equivalence verification and ECO methodology. Strong Hands on experience and in Synopsys DC, DCRT, Fusion compiler Front end for logic synthesis, Cadence Conformal LEC for verification and Cadence Genus - Hand on experience on verifying difference between POST ECO and PRE ECO netlists, generate path files and apply them to pre ECO netlist, Synthesize netlist from Pre-Eco netlist. - Experience with TCL/Perl/Shell programming. Experience in design automation and enhancement of new features - Good understanding of full chip level level Synthesis, sign off and verification methodologies - Deep understanding of process technology at 14nm and below and low power methodology Inside this Business Group The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
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